Fundamental to the fabrication of integrated circuits is the formation of metallization layers to establish electrical communication within the circuit, as well as to external circuitry. A "chip level" interconnect is a metallization layer for electrically connecting device electrodes, e.g. source, drain, gate, base, emitter or collector. A "packaging" interconnect is a metallization layer to provide electrical contact between a chip level interconnect and an input/output lead.
On a large scale, aluminum metallization is typically used as the interconnect layer at both the chip and packaging levels. Aluminum is easily vacuum-deposited and has a high conductivity. Aluminum alloys may also be chosen for different performance-related reasons. Particularly in the area of packaging interconnects, a well-developed technology exists for the deposition and patterning of these metallization layers.
As circuit density increases, the contact area of a device electrode becomes one of the limiting factors for circuit density and performance. A local interconnect is a chip level interconnect that increases circuit density by providing contact between local polysilicon gate and source/drain regions, as well as contact between intra-device source/drain regions, without requiring the formation of contact holes. By eliminating the need for contact holes, the local interconnects reduce parasitic capacitance and enhance circuit performance.
While local interconnects provide improvements in semiconductor integrated circuit chip technology, process complexities and control difficulties have limited the use of local interconnects. U.S. Pat. No. 4,957,590 to Douglas describes alternative methods of forming local interconnects. One described method, credited as a Hewlett-Packard Corporation invention, is to use a silicide as the local interconnect material. A layer of titanium is deposited over a substrate and, prior to the direct reaction of the titanium with any underlying silicon and polysilicon to form titanium silicide, a thin layer of amorphous silicon is patterned on top of the titanium metal to define an interconnect extending over a silicon dioxide region separating two electrode regions to be interconnected. The patterned silicon layer forms a silicide across the silicon dioxide region upon reacting of the titanium with the silicon. One potential difficulty with this method is that it requires deposition and patterning of an additional layer of silicon to define the local interconnections. A second difficulty is that the titanium silicide is a poor diffusion barrier to conventional semiconductor dopants, such as phosphorous and arsenic. Thus, where the silicide is used to connect n-type regions to p-type regions, any subsequent processing must be performed at relatively low temperatures to minimize the counterdoping that potentially could take place through the silicide interconnect.
The Douglas patent teaches that titanium nitride is a preferred material for forming local interconnects, but that using standard fluorine-based chemistries in plasma etching the titanium nitride provides unacceptable selectivity for achieving submicron geometries. The Douglas patent notes that carbon tetrafluoride (CF.sub.4) etches titanium nitride at twice the rate of titanium silicide, but also etches silicon oxides and photoresists at a rate faster than the titanium nitride. To increase selectivity, Douglas teaches use of a chlorine-bearing agent as a plasma etchant. However, titanium nitride can be difficult to deposit, so that submicron geometries are still difficult to achieve.
Titanium-tungsten is another possible material for fabrication of local interconnects. However, titanium-tungsten is unstable with respect to oxidation. Formation of a local interconnect is followed by fabrication steps which inevitably require high temperatures, such as formation of phosphosilicate glass layers at a temperature of 800.degree. C. The inherent instability of titanium-tungsten with respect to oxidation would result in reactions occurring in the titanium-tungsten film to form a titanium oxide and a tungsten oxide. Because oxidation affects the resistivity of the film, the performance of the integrated circuit would be adversely affected.
It is an object of the present invention to provide a method of forming interconnects, particularly interconnects that contact exposed regions of a semiconductor wafer, wherein the formed interconnects are stable with respect to oxidation and have a low, reproducible sheet resistance and wherein the method is not critically dependent upon process parameters and requires no new tools or technologies. It is a further object to provide a method to form such interconnects that exhibit increased diffusion-inhibiting characteristics.